AC82G41SLGQ3 Datasheet, PDF (471/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
Access
31:16
W
15:0
R/W
Default
Value
0000h
0000h
RST/PWR
Description
Core
Core
Source ID (SID): This field indicates the source-ID of the
device whose corresponding context-entry needs to be
selectively invalidated. This field along with the FM field
must be programmed by software for device-selective
invalidation requests.
Value returned on read of this field is undefined.
Domain-ID (DID): This field indicates the id of the
domain whose context-entries needs to be selectively
invalidated. This field must be programmed by software
for both domain-selective and device-selective invalidation
requests.
The Capability register reports the domain-ID width
supported by hardware. Software must ensure that the
value written to this field is within this limit.
Hardware may ignore and not implement bits 15:N where
N is the supported domain-ID width reported in the
capability register.
12.2.8
FSTS_REG—Fault Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIVC1REMAP
34-37h
00000000h
RO, RO/P, R/WC/P
32 bits
This register indicates the primary fault logging status.
Bit
31:16
Access
RO
15:8
RO/P
7
RO
6
RO
Default
Value
0000h
00h
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Reserved
Fault Record Index (FRI): This field is valid only when
the PPF field is set.
The FRI field indicates the index (from base) of the fault
recording register to which the first pending fault was
recorded when the PPF field was set by hardware.
Valid values for this field are from 0 to N, where N is the
value reported through NFR field in the Capability register.
The value read from this field is undefined when the PPF
field is clear.
Reserved
Invalidation Time-out Error (ITE): Hardware detected
a Device-IOTLB invalidation completion time-out. At this
time, a fault event may be generated based on the
programming of the Fault Event Control register.
Hardware implementations not supporting Device-IOTLBs
implement this bit as Reserved.
NOTE: This field is reserved as this feature is not
supported.
Datasheet
471