AC82G41SLGQ3 Datasheet, PDF (327/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.1.23 MUA— Message Signaled Interrupt Upper Address
(Optional)
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/0/PCI
94-97h
00000000h
R/W
32 bits
Bit
31:0
Access
R/W
Default
Value
00000000h
RST/PWR
Description
Core
Upper Address (UADDR): Upper 32 bits of the system
specified message address. This register is optional and
only implemented if MC.C64=1.
10.1.24 MD— Message Signaled Interrupt Message Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/0/PCI
98-99h
0000h
R/W
16 bits
Bit
15:0
Access
R/W
Default
Value
0000h
RST/PWR
Description
Core
Data (Data): This 16-bit field is programmed by system
software if MSI is enabled. Its content is driven onto the
FSB during the data phase of the MSI memory write
transaction.
Datasheet
327