AC82G41SLGQ3 Datasheet, PDF (253/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.34
PE_CAP—PCI Express* Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
A2–A3h
0142h
RO, RWO
16 bits
This register indicates PCI Express device capabilities.
Bit
15:14
13:9
8
7:4
3:0
Access
RO
RO
RWO
RO
RO
Default
Value
00b
00h
1b
4h
2h
RST/
PWR
Core
Core
Core
Core
Core
Description
Reserved
Interrupt Message Number (IMN): Not Applicable or
Implemented. Hardwired to 0.
Slot Implemented (SI):
0 = The PCI Express Link associated with this port is connected to an
integrated component or is disabled.
1 = The PCI Express Link associated with this port is connected to a
slot.
Device/Port Type (DPT): Hardwired to 4h to indicate root port of
PCI Express Root Complex.
PCI Express Capability Version (PCIECV): Hardwired to 2h to
indicate compliance to the PCI Express Capabilities Register
Expansion ECN.
8.35
DCAP—Device Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
A4–A7h
00008000h
RO
32 bits
This register indicates PCI Express device capabilities.
Bit
31:16
15
14:6
5
4:3
2:0
Access
RO
RO
RO
RO
RO
RO
Default
Value
0000h
1b
000h
0b
00b
000b
RST/
PWR
Core
Core
Core
Core
Core
Core
Description
Reserved
Role Based Error Reporting (RBER): This bit indicates that this
device implements the functionality defined in the Error Reporting
ECN as required by the PCI Express 1.1 specification.
Reserved
Extended Tag Field Supported (ETFS): Hardwired to indicate
support for 5-bit Tags as a Requestor.
Phantom Functions Supported (PFS): Not Applicable or
Implemented. Hardwired to 0.
Max Payload Size (MPS): Hardwired to indicate 128B max
supported payload for Transaction Layer Packets (TLP).
Datasheet
253