AC82G41SLGQ3 Datasheet, PDF (492/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
Access
22
RO
21:16
RO
15:13
RO
12:8
RO
Default
Value
1b
23h
0h
02h
RST/PWR
Description
Core
Core
Core
Core
Zero Length Read (ZLR):
0 = Remapping hardware unit blocks (and treats as fault)
zero length DMA read requests to write-only pages.
1 = Remapping hardware unit supports zero length DMA
read requests to write-only pages.
Maximum Guest Address Width (MGAW): This field
indicates the maximum DMA virtual addressability
supported by remapping hardware.
The Maximum Guest Address Width (MGAW) is computed
as (N+1), where N is the value reported in this field. For
example, a hardware implementation supporting 48-bit
MGAW reports a value of 47 (101111b) in this field.
If the value in this field is X, DMA requests to addresses
above 2(x+1)-1 are always blocked by hardware.
Guest addressability for a given DMA request is limited to
the minimum of the value reported through this field and
the adjusted guest address width of the corresponding
page-table structure. (Adjusted guest address widths
supported by hardware are reported through the SAGAW
field).
Reserved
Supported adjusted guest address width (SAGAW):
This 5-bit field indicates the supported adjusted guest
address widths (which in turn represents the levels of
page-table walks) supported by the hardware
implementation.
A value of 1 in any of these bits indicates the
corresponding adjusted guest address width is supported.
The adjusted guest address widths corresponding to
various bit positions within this field are:
0 = 30-bit AGAW (2-level page table)
1 = 39-bit AGAW (3-level page table)
2 = 48-bit AGAW (4-level page table)
3 = 57-bit AGAW (5-level page table)
4 = 64-bit AGAW (6-level page table)
Software must ensure that the adjusted guest address
width used to setup the page tables is one of the supported
guest address widths reported in this field.
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Datasheet