AC82G41SLGQ3 Datasheet, PDF (40/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Signal Description
2.2.2 System Memory Channel B Interface Signals
Signal Name
DDR_B_CK
DDR_B_CKB
DDR_B_CSB_[3:0]
Type
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
Description
SDRAM Differential Clocks:
• DDR2: Three per DIMM
• DDR3: Two per DIMM
SDRAM Inverted Differential Clocks:
• DDR2: Three per DIMM
• DDR3: Two per DIMM
DDR2/DDR3 Device Rank 3, 2, 1, and 0 Chip
Select
DDR_B_CKE_[3:0]
O
DDR2/DDR3 Clock Enable:
SSTL-1.8/1.5 (1 per Device Rank)
DDR_B_ODT_[3:0]
DDR_B_MA_[14:0]
DDR_B_BS_[2:0]
DDR_B_RASB
DDR_B_CASB
DDR_B_WEB
DDR_B_DQ_[63:0]
DDR_B_DM_[7:0]
DDR_B_DQS_[7:0]
DDR_B_DQSB_[7:0]
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
I/O
SSTL-1.8/1.5
O
SSTL-1.8/1.5
I/O
SSTL-1.8/1.5
I/O
SSTL-1.8/1.5
DDR2/DDR3 Device Rank 3, 2, 1, and 0 On Die
Termination
DDR2/DDR3 Address Signals [14:0]
DDR2/DDR3 Bank Select
DDR2/DDR3 Row Address Select signal
DDR2/DDR3 Column Address Select signal
DDR2/DDR3 Write Enable signal
DDR2/DDR3 Data Lines
DDR2/DDR3 Data Mask
DDR2/DDR3 Data Strobes
DDR2/DDR3 Data Strobe Complements
40
Datasheet