AC82G41SLGQ3 Datasheet, PDF (107/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.23
Note:
PAM5—Programmable Attribute Map 5
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
95h
00h
RO, R/W/L
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E0000h–0E7FFFh.
All the bits in this register are locked in Intel TXT mode (82Q45/82Q43 GMCH only).
Bit
Access
Default
Value
RST/PWR
Description
7:6
RO
00b
5:4
R/W/L
00b
3:2
RO
00b
1:0
R/W/L
00b
Core
Core
Core
Core
Reserved
0E4000h-0E7FFFh Attribute (HIENABLE): This field
controls the steering of read and write cycles that address
the BIOS area from 0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes
are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are
serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are
serviced by DRAM.
Reserved
0E0000-0E3FFF Attribute (LOENABLE): This field
controls the steering of read and write cycles that
address the BIOS area from 0E0000 to 0E3FFF.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes
are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are
serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are
serviced by DRAM.
Datasheet
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