AC82G41SLGQ3 Datasheet, PDF (234/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.4
PCISTS1—PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
6–7h
0010h
RO, RWC
16 bits
This register reports the occurrence of error conditions associated with primary side of
the "virtual" Host-PCI Express bridge embedded within the MCH.
Bit
15
14
13
12
11
10:9
8
7
6
5
4
Access
RO
RWC
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
0b
00b
0b
0b
0b
0b
1b
RST/
PWR
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Description
Detected Parity Error (DPE): Not Applicable or Implemented.
Hardwired to 0. Parity (generating poisoned Transaction Layer
Packets) is not supported on the primary side of this device.
Signaled System Error (SSE): This bit is set when this Device sends
a SERR due to detecting an ERR_FATAL or ERR_NONFATAL condition
and the SERR Enable bit in the Command register is 1. Both received
(if enabled by BCTRL1[1]) and internally detected error messages do
not affect this field).
Received Master Abort Status (RMAS): Not Applicable or
Implemented. Hardwired to 0. The concept of a master abort does not
exist on primary side of this device.
Received Target Abort Status (RTAS): Not Applicable or
Implemented. Hardwired to 0. The concept of a target abort does not
exist on primary side of this device.
Signaled Target Abort Status (STAS): Not Applicable or
Implemented. Hardwired to 0. The concept of a target abort does not
exist on primary side of this device.
DEVSELB Timing (DEVT): This device is not the subtractively
decoded device on bus 0. This bit field is therefore hardwired to 00 to
indicate that the device uses the fastest possible decode.
Master Data Parity Error (PMDPE): Because the primary side of
the PCI Express's virtual peer-to-peer bridge is integrated with the
MCH functionality, there is no scenario where this bit will get set.
Because hardware will never set this bit, it is impossible for software
to have an opportunity to clear this bit or otherwise test that it is
implemented. The PCI specification defines it as a R/WC, but for our
implementation an RO definition behaves the same way and will meet
all Microsoft testing requirements.
This bit can only be set when the Parity Error Enable bit in the PCI
Command register is set.
Fast Back-to-Back (FB2B): Not Applicable or Implemented.
Hardwired to 0.
Reserved
66/60MHz capability (CAP66): Not Applicable or Implemented.
Hardwired to 0.
Capabilities List (CAPL): Indicates that a capabilities list is present.
Hardwired to 1.
234
Datasheet