AC82G41SLGQ3 Datasheet, PDF (263/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
Bit
Access
Default
Value
RST/
PWR
Description
7:6
RO
5:4
RO
3
RW
2
RO
1
RO
0
RO
Attention Indicator Control (AIC): If an Attention Indicator is
implemented, writes to this field set the Attention Indicator to the
written state.
Reads of this field must reflect the value from the latest write, unless
software issues a write without waiting for the previous command to
complete in which case the read value is undefined. If the indicator is
electrically controlled by chassis, the indicator is controlled directly by
00b
Core _{the downstream port through implementation specific mechanisms.}
00 = Reserved
01 = On
10 = Blink
11 = Off
If the Attention Indicator Present bit in the Slot Capabilities register is
0b, this field is permitted to be read only with a value of 00b.
00b
Core Reserved
0b
Core
Presence Detect Changed Enable (PDCE): When set to 1b, this bit
enables software notification on a presence detect changed event.
MRL Sensor Changed Enable (MSCE): When set to 1b, this bit
enables software notification on a MRL sensor changed event.
0b
Core Default value of this field is 0b. If the MRL Sensor Present field in the
Slot Capabilities register is set to 0b, this bit is permitted to be read-
only with a value of 0b.
Power Fault Detected Enable (PFDE): When set to 1b, this bit
enables software notification on a power fault event.
0b
Core
Default value of this field is 0b. If Power Fault detection is not
supported, this bit is permitted to be read-only with a value of 0b
0b
Core
Button Pressed Enable (ABPE): When set to 1b, this bit enables
software notification on an attention button pressed event.
Datasheet
263