AC82G41SLGQ3 Datasheet, PDF (142/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.21
C1CYCTRKPCHG—Channel 1 CYCTRK PCHG
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
650-651h
0000h
R/W, RO
16 bits
Bit
15:11
Access
RO
10:6
R/W
5:2
R/W
1:0
R/W
Default
Value
00000b
00000b
0000b
00b
RST/PWR
Description
Core
Core
Core
Core
Reserved.
Write To PRE Delayed (C1sd_cr_wr_pchg): This field
indicates the minimum allowed spacing (in DRAM clocks)
between the WRITE and PRE commands to the same rank-
bank. This field corresponds to tWR in the DDR
Specification.
READ To PRE Delayed (C1sd_cr_rd_pchg): This field
indicates the minimum allowed spacing (in DRAM clocks)
between the READ and PRE commands to the same rank-
bank
PRE To PRE Delayed (C1sd_cr_pchg_pchg): This field
indicates the minimum allowed spacing (in DRAM clocks)
between two PRE commands to the same rank.
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Datasheet