AC82G41SLGQ3 Datasheet, PDF (223/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Direct Memory Interface Registers (DMIBAR)
Bit
16:8
7:1
0
7.7
Bit
15:2
1
0
Access
RO
R/W
RO
Default
Value
000h
7Fh
1b
RST/PWR
Description
Core
Core
Core
Reserved
Traffic Class / Virtual Channel 0 Map (TCVC0M): This
field indicates the TCs (Traffic Classes) that are mapped to
the VC resource. Bit locations within this field correspond
to TC values.
For example, when bit 7 is set in this field, TC7 is mapped
to this VC resource. When more than one bit in this field is
set, it indicates that multiple TCs are mapped to the VC
resource. To remove one or more TCs from the TC/VC Map
of an enabled VC, software must ensure that no new or
outstanding transactions with the TC labels are targeted at
the given Link.
Traffic Class 0 / Virtual Channel 0 Map (TC0VC0M):
Traffic Class 0 is always routed to VC0.
DMIVC0RSTS—DMI VC0 Resource Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
1A-1Bh
0002h
RO
16 bits
This register reports the Virtual Channel specific status.
Access
RO
RO
RO
Default
Value
0000h
1b
0b
RST/PWR
Description
Core
Core
Core
Reserved: Reserved and Zero for future R/WC/S
implementations. Software must use 0 for writes to these
bits.
Virtual Channel 0 Negotiation Pending (VC0NP):
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation
(initialization or disabling).
This bit indicates the status of the process of Flow Control
initialization. It is set by default on Reset, as well as
whenever the corresponding Virtual Channel is Disabled or
the Link is in the DL_Down state.
It is cleared when the link successfully exits the FC_INIT2
state.
BIOS Requirement: Before using a Virtual Channel,
software must check whether the VC Negotiation Pending
fields for that Virtual Channel are cleared in both
Components on a Link.
Reserved
Datasheet
223