AC82G41SLGQ3 Datasheet, PDF (227/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Direct Memory Interface Registers (DMIBAR)
7.11
DMILCAP—DMI Link Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
84-87h
00012C41h
RO, R/WO
32 bits
This register indicates DMI specific capabilities.
Bit
31:18
Access
RO
17:15
R/WO
14:12
11:10
9:4
3:0
R/WO
RO
RO
RO
Default
Value
0000h
010b
010b
11b
04h
1h
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Reserved
L1 Exit Latency (L1SELAT): This field indicates the
length of time this Port requires to complete the transition
from L1 to L0. The value 010 b indicates the range of 2 us
to less than 4 us.
000 = Less than 1µs
001 = 1 µs to less than 2 µs
010 = 2 µs to less than 4 µs
011 = 4 µs to less than 8 µs
100 = 8 µs to less than 16 µs
101 = 16 µs to less than 32 µs
110 = 32 µs–64 µs
111 = More than 64 µs
Both bytes of this register that contain a portion of this
field must be written simultaneously in order to prevent an
intermediate (and undesired) value from ever existing.
Reserved
Active State Link PM Support (ASLPMS): L1 entry
supported.
Max Link Width (MLW): This field indicates the
maximum number of lanes supported for this link.
Max Link Speed (MLS): Hardwired to indicate 2.5 Gb/s.
Datasheet
227