AC82G41SLGQ3 Datasheet, PDF (89/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
2
1
0
5.1.4
Access
RO
Default
Value
1b
RO
1b
RO
0b
RST/
PWR
Core
Core
Core
Description
Bus Master Enable (BME): The (G)MCH is always
enabled as a master on the backbone. This bit is hardwired
to a 1.
Memory Access Enable (MAE): The (G)MCH always
allows access to main memory. This bit is not implemented
and is hardwired to 1.
I/O Access Enable (IOAE): This bit is not implemented
in the (G)MCH and is hardwired to a 0.
PCISTS—PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
6-7h
0090h
RO, R/WC
16 bits
This status register reports the occurrence of error events on Device 0's PCI interface.
Since the (G)MCH Device 0 does not physically reside on PCI_A many of the bits are
not implemented.
Bit
Access
Default
Value
15
R/WC
0b
14
R/WC
0b
13
R/WC
0b
12
R/WC
0b
11
RO
0b
10:9
RO
00b
RST/
PWR
Core
Core
Core
Core
Core
Core
Description
Detected Parity Error (DPE): This bit is set when this
Device receives a Poisoned TLP.
Signaled System Error (SSE): This bit is set to 1 when
the (G)MCH Device 0 generates an SERR message over
DMI for any enabled Device 0 error condition. Device 0
error conditions are enabled in the PCICMD, ERRCMD, and
DMIUEMSK registers. Device 0 error flags are read/reset
from the PCISTS, ERRSTS, or DMIUEST registers.
Software clears this bit by writing a 1 to it.
Received Master Abort Status (RMAS): This bit is set
when the (G)MCH generates a DMI request that receives
an Unsupported Request completion packet. Software
clears this bit by writing a 1 to it.
Received Target Abort Status (RTAS): This bit is set
when the (G)MCH generates a DMI request that receives a
Completer Abort completion packet. Software clears this
bit by writing a 1 to it.
Signaled Target Abort Status (STAS): The (G)MCH will
not generate a Target Abort DMI completion packet or
Special Cycle. This bit is not implemented in the (G)MCH
and is hardwired to a 0. Writes to this bit position have no
effect.
DEVSEL Timing (DEVT): These bits are hardwired to
"00". Writes to these bit positions have no affect. Device 0
does not physically connect to PCI_A. These bits are set to
"00" (fast decode) so that optimum DEVSEL timing for
PCI_A is not limited by the (G)MCH.
Datasheet
89