AC82G41SLGQ3 Datasheet, PDF (292/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.1.24
SSRW—Software Scratch Read Write
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
58-5Bh
00000000h
R/W
32 bits
Bit
31:0
Access
R/W
Default
Value
00000000h
RST/PWR
FLR, Core Reserved
Description
9.1.25
BSM—Base of Stolen Memory
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
5C-5Fh
07800000h
RO
32 bits
Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From
the top of low used DRAM, GMCH claims 1 to 64 MB of DRAM for internal graphics if
enabled.
The base of stolen memory will always be below 4 GB. This is required to prevent
aliasing between stolen range and the reclaim region.
Bit
Access
31:20
RO
19:0
RO
Default
Value
078h
00000h
RST/PWR
Description
Core
Core
Base of Stolen Memory (BSM): This register contains
bits 31:20 of the base address of stolen DRAM memory.
The host interface determines the base of Graphics Stolen
memory by subtracting the graphics stolen memory size
from TOLUD. See Device 0 TOLUD for more explanation.
Reserved
9.1.26
HSRW—Hardware Scratch Read Write
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
60-61h
0000h
R/W
16 bits
Bit
15:0
Access
R/W
Default
Value
0000h
RST/PWR
FLR, Core Reserved
Description
292
Datasheet