AC82G41SLGQ3 Datasheet, PDF (121/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.38
SMICMD—SMI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
CC-CDh
0000h
RO, R/W
16 bits
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively. Note that one and only one message type can be enabled.
Bit
15:12
Access
RO
11
R/W
10:2
RO
1
R/W
0
R/W
Default
Value
0h
0b
000h
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Reserved
SMI on (G)MCH Thermal Sensor Trip (TSTSMI):
1 = A SMI DMI special cycle is generated by (G)MCH when
the thermal sensor trip requires an SMI. A thermal
sensor trip point cannot generate more than one
special cycle.
0 = Reporting of this condition via SMI messaging is
disabled.
Reserved
SMI on Multiple-Bit DRAM ECC Error (DMESMI):
1 = The (G)MCH generates an SMI DMI message when it
detects a multiple-bit error reported by the DRAM
controller.
0 = Reporting of this condition via SMI messaging is
disabled. For systems not supporting ECC this bit
must be disabled.
SMI on Single-bit ECC Error (DSESMI):
1 = The (G)MCH generates an SMI DMI special cycle when
the DRAM controller detects a single bit error.
0 = Reporting of this condition via SMI messaging is
disabled. For systems that do not support ECC this bit
must be disabled.
Datasheet
121