AC82G41SLGQ3 Datasheet, PDF (336/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.2.17 PC— PCI Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
52-53h
C803h
RO
16 bits
Bit
Access
15:11
RO
10
RO
9
RO
8:6
RO
5
RO
4
RO
3
RO
2:0
RO
Default
Value
11001b
0b
0b
000b
0b
0b
0b
011b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
PME_Support (PSUP): This field indicates the states that
can generate PME#.
HECI can assert PME# from any D-state except D1 or D2
which are not supported by HECI.
D2_Support (D2S): The D2 state is not supported for the
HECI host controller.
D1_Support (D1S): The D1 state is not supported for the
HECI host controller.
Aux_Current (AUXC): This field reports the maximum
Suspend well current required when in the D3COLD state.
Device Specific Initialization (DSI): This bit indicates
whether device-specific initialization is required.
Reserved
PME Clock (PMEC): This bit indicates that PCI clock is not
required to generate PME#.
Version (VS): Indicates support for the PCI Power
Management Specification, Revision 1.2.
336
Datasheet