AC82G41SLGQ3 Datasheet, PDF (249/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.26
PM_CS1—Power Management Control/Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
84–87h
00000008h
RO, RW, RW/P
32 bits
Bit
31:16
15
14:13
12:9
8
7:2
1:0
Access
RO
RO
RO
RO
RW/P
RO
RW
Default
Value
0000h
0b
00b
0h
0b
0000b
00b
RST/
PWR
Core
Core
Core
Core
Core
Core
Core
Description
Reserved
PME Status (PMESTS): This bit indicates that this device does not
support PMEB generation from D3cold.
Data Scale (DSCALE): This field indicates that this device does not
support the power management data register.
Data Select (DSEL): This field indicates that this device does not
support the power management data register.
PME Enable (PMEE): This bit indicates that this device does not
generate PMEB assertion from any D-state.
0 = PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
Reserved
Power State (PS): This field indicates the current power state of this
device and can be used to set the device into a new power state. If
software attempts to write an unsupported state to this field, write
operation must complete normally on the bus, but the data is
discarded and no state change occurs.
00 = D0
01 = D1 (Not supported in this device.)
10 = D2 (Not supported in this device.)
11 = D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of PCI
configuration transactions (for power management control). This
device also cannot generate interrupts or respond to MMR cycles in
the D3 state. The device must return to the D0 state in order to be
fully-functional.
When the Power State is other than D0, the bridge will Master Abort
(i.e. not claim) any downstream cycles (with exception of type 0
config cycles). Consequently, these unclaimed cycles will go down DMI
and come back up as Unsupported Requests, which the MCH logs as
Master Aborts in Device 0 PCISTS[13]
There is no additional hardware functionality required to support these
Power States.
Datasheet
249