AC82G41SLGQ3 Datasheet, PDF (110/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
Access
Default
Value
RST/
PWR
Description
PEG0 MDA Present (MDAP0): This bit works with the
VGA Enable bits in the BCTRL register of Device 1 to
control the routing of processor-initiated transactions
targeting MDA compatible I/O and memory address
ranges. This bit should not be set if device 1's VGA
Enable bit is not set.
If device 1's VGA enable bit is not set, then accesses to
I/O address range x3BCh–x3BFh are forwarded to DMI.
If the VGA enable bit is set and MDA is not present, then
accesses to IO address range x3BCh–x3BFh are
forwarded to PCI Express if the address is within the
corresponding IOBASE and IOLIMIT, otherwise they are
forwarded to DMI.
MDA resources are defined as the following:
Memory: 0B0000h–0B7FFFh
I/O:
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are
not used in decode)
0
R/W
0b
Core Any I/O reference that includes the I/O locations listed
above, or their aliases, will be forwarded to the DMI even
if the reference includes I/O locations not listed above.
The following table shows the behavior for all
combinations of MDA and VGA:
VGAEN MDAP Description
0
0
All References to MDA and VGA space
are routed to DMI
0
1
invalid combination
1
0
All VGA and MDA references are
routed to PCI Express Graphics
Attach.
1
1
All VGA references are routed to PCI
Express Graphics Attach. MDA
references are routed to DMI.
VGA and MDA memory cycles can only be routed across
the PEG when MAE (PCICMD1[1]) is set. VGA and MDA I/
O cycles can only be routed across the PEG if IOAE
(PCICMD1[0]) is set.
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