AC82G41SLGQ3 Datasheet, PDF (474/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
30
29:0
Access
RO
RO
Default
Value
0h
00000000h
RST/PWR
Description
Core
Core
Interrupt Pending (IP): Hardware sets the IP field
whenever it detects an interrupt condition. Interrupt
condition is defined as:
• When primary fault logging is active, an interrupt
condition occurs when hardware records a fault
through one of the Fault Recording registers and sets
the PPF field in Fault Status register. If the PPF field was
already set at the time of recording a fault, it is not
treated as a new interrupt condition.
• When advanced fault logging is active, an interrupt
condition occurs when hardware records a fault in the
first fault record (at index 0) of the current fault log
and sets the APF field in the Advanced Fault Log
register. If the APF field was already set at the time of
detecting/recording a fault, it is not treated as a new
interrupt condition.
The IP field is kept set by hardware while the interrupt
message is held pending. The interrupt message could be
held pending due to interrupt mask (IM field) being set, or
due to other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt
message pending condition is serviced. This could be due
to either:
• Hardware issuing the interrupt message due to either
change in the transient hardware condition that caused
interrupt message to be held pending or due to
software clearing the IM field.
• Software servicing the interrupting condition through
one of the following ways:
— When primary fault logging is active, software
clearing the Fault (F) field in all the Fault Recording
registers with faults, causing the PPF field in Fault
Status register to be evaluated as clear.
— When advanced fault logging is active, software
clearing the APF field in Advanced Fault Log
register.
Reserved
474
Datasheet