AC82G41SLGQ3 Datasheet, PDF (334/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.2.11 CAP— Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
34h
50h
RO
8 bits
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
Capability Pointer (CP): This field indicates the first
50h
Core
capability pointer offset. It points to the PCI power
management capability offset.
10.2.12 INTR— Interrupt Information
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
3C-3Dh
0100h
R/W, RO
16 bits
Bit
15:8
7:0
Access
RO
R/W
Default
Value
01h
00h
RST/PWR
Description
Core
Core
Interrupt Pin (IPIN): This field indicates the interrupt
pin the HECI host controller uses. The value of 01h selects
INTA# interrupt pin.
NOTE: As HECI is an internal device in the (G)MCH, the
INTA# pin is implemented as an INTA# message to
the ICH.
Interrupt Line (ILINE): Software written value to
indicate which interrupt line (vector) the interrupt is
connected to. No hardware action is taken on this register.
10.2.13 MGNT— Minimum Grant
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
3Eh
00h
RO
8 bits
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
00h
Core
Grant (GNT): Not implemented, hardwired to 0.
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Datasheet