AC82G41SLGQ3 Datasheet, PDF (207/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
Bit
Access
Default
Value
RST/PWR
Description
11
RO
10
RO
9:4
RO
3:0
RO
Link Training (LTRN): This bit indicates that the Physical
Layer LTSSM is in the Configuration or Recovery state, or
0b
Core
that 1b was written to the Retrain Link bit but Link training
has not yet begun. Hardware clears this bit when the
LTSSM exits the Configuration/Recovery state once Link
training is complete.
Undefined (Undefined): The value read from this bit is
undefined. In previous versions of this specification, this
0b
Core
bit was used to indicate a Link Training Error. System
software must ignore the value read from this bit. System
software is permitted to write any value to this bit.
Negotiated Link Width (NLW): This field indicates
negotiated link width. This field is valid only when the link
is in the L0 or L1 states (after link width negotiation is
successfully completed).
00h = Reserved
00h
Core
01h = X1
02h = X2
04h = X4
08h = X8
10h = X16
All other encodings are reserved.
Current Link Speed (CLS): This field indicates the
negotiated Link speed of the given PCI Express Link.
0001b = 2.5 GT/s PCI Express Link
0h
Core
0010b = 5 GT/s PCI Express Link
All other encodings are reserved. The value in this field is
undefined when the Link is not up.
Datasheet
207