AC82G41SLGQ3 Datasheet, PDF (88/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.3
PCICMD—PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
4-5h
0006h
RO, R/W
16 bits
Since (G)MCH Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
Bit
15:10
Access
RO
Default
Value
00h
9
RO
0b
8
R/W
0b
7
RO
0b
6
R/W
0b
5
RO
0b
4
RO
0b
3
RO
0b
RST/
PWR
Core
Core
Core
Core
Core
Core
Core
Core
Description
Reserved
Fast Back-to-Back Enable (FB2B): This bit controls
whether or not the master can do fast back-to-back write.
Since device 0 is strictly a target this bit is not
implemented and is hardwired to 0. Writes to this bit
position have no effect.
SERR Enable (SERRE): This bit is a global enable bit for
Device 0 SERR messaging. The (G)MCH does not have an
SERR signal. The (G)MCH communicates the SERR
condition by sending an SERR message over DMI to the
ICH.
1 = The (G)MCH is enabled to generate SERR messages
over DMI for specific Device 0 error conditions that are
individually enabled in the ERRCMD and DMIUEMSK
registers. The error status is reported in the ERRSTS,
PCISTS, and DMIUEST registers.
0 = The SERR message is not generated by the (G)MCH for
Device 0.
Note that this bit only controls SERR messaging for the
Device 0. Device 1 has its own SERRE bits to control error
reporting for error conditions occurring in that device. The
control bits are used in a logical OR manner to enable the
SERR DMI message mechanism.
Address/Data Stepping Enable (ADSTEP): Address/
data stepping is not implemented in the (G)MCH, and this
bit is hardwired to 0. Writes to this bit position have no
effect.
Parity Error Enable (PERRE): Controls whether or not
the Master Data Parity Error bit in the PCI Status register
can bet set.
0 = Master Data Parity Error bit in PCI Status register can
NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN
be set.
VGA Palette Snoop Enable (VGASNOOP): The (G)MCH
does not implement this bit and it is hardwired to a 0.
Memory Write and Invalidate Enable (MWIE): The
(G)MCH will never issue memory write and invalidate
commands. This bit is therefore hardwired to 0.
Special Cycle Enable (SCE): The (G)MCH does not
implement this bit and it is hardwired to a 0.
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