AC82G41SLGQ3 Datasheet, PDF (191/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.24
BCTRL1—Bridge Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
3E-3Fh
0000h
RO, R/W
16 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (i.e., PCI
Express) as well as some bits that affect the overall behavior of the "virtual" Host-PCI
Express bridge in the (G)MCH (e.g., VGA compatible address ranges mapping).
Bit
15:12
11
10
9
8
7
Access
RO
RO
RO
RO
RO
RO
6
R/W
5
RO
4
R/W
3
R/W
Default
Value
0h
0b
0b
0b
0b
0b
0b
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Reserved
Discard Timer SERR# Enable (DTSERRE): Not
Applicable or Implemented. Hardwired to 0.
Discard Timer Status (DTSTS): Not Applicable or
Implemented. Hardwired to 0.
Secondary Discard Timer (SDT): Not Applicable or
Implemented. Hardwired to 0.
Primary Discard Timer (PDT): Not Applicable or
Implemented. Hardwired to 0.
Fast Back-to-Back Enable (FB2BEN): Not Applicable or
Implemented. Hardwired to 0.
Secondary Bus Reset (SRESET): Setting this bit
triggers a hot reset on the corresponding PCI Express Port.
This will force the LTSSM to transition to the Hot Reset
state (via Recovery) from L0 or L1 states.
Master Abort Mode (MAMODE): Does not apply to PCI
Express. Hardwired to 0.
VGA 16-bit Decode (VGA16D): Enables the PCI-to-PCI
bridge to provide 16-bit decoding of VGA I/O address
precluding the decoding of alias addresses every 1 KB.
This bit only has meaning if bit 3 (VGA Enable) of this
register is also set to 1, enabling VGA I/O decoding and
forwarding by the bridge.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
VGA Enable (VGAEN): This bit controls the routing of
processor-initiated transactions targeting VGA compatible
I/O and memory address ranges. See the VGAEN/MDAP
table in device 0, offset 97h[0].
Datasheet
191