AC82G41SLGQ3 Datasheet, PDF (290/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.1.23
Note:
DEVEN—Device Enable
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
54-57h
000023DBh
RO
32 bits
This register allows for enabling/disabling of PCI devices and functions that are within
the GMCH.
All the bits in this register are locked in Intel TXT mode (82Q45/82Q43 GMCH only).
Bit
31:15
14
13
12:11
10
Access
RO
RO
RO
RO
RO
Default
Value
00000h
0b
1b
00b
0b
9
RO
1b
8
RO
1b
7
RO
1b
6
RO
1b
5
RO
0b
RST/
PWR
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Description
Reserved
Reserved
Reserved
Reserved (DEVEN):
Reserved (D3F4EN):
EP Function 3 (D3F3EN):
0 = Bus 0, Device 3, Function 3 is disabled and hidden
1 = Bus 0, Device 3, Function 3 is enabled and visible
If Device 3, Function 0 is disabled and hidden, then Device 3,
Function 3 is also disabled and hidden independent of the state
of this bit.
EP Function 2 (D3F2EN):
0 = Bus 0, Device 3, Function 2 is disabled and hidden
1 = Bus 0, Device 3, Function 2 is enabled and visible
If Device 3, Function 0 is disabled and hidden, then Device 3,
Function 2 is also disabled and hidden independent of the state
of this bit.
EP Function 1 (D3F1EN):
0 = Bus 0, Device 3, Function 1 is disabled and hidden
1 = Bus 0, Device 3, Function 1 is enabled and visible.
If this GMCH does not have ME capability (CAPID0[??] = 1), then
Device 3, Function 1 is disabled and hidden independent of the
state of this bit.
EP Function 0 (D3F0EN):
0 = Bus 0, Device 3, Function 0 is disabled and hidden
1 = Bus 0, Device 3, Function 0 is enabled and visible.
If this GMCH does not have ME capability (CAPID0[??] = 1) then
Device 3, Function 0 is disabled and hidden independent of the
state of this bit.
Reserved
290
Datasheet