AC82G41SLGQ3 Datasheet, PDF (476/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.2.12 FEUADDR_REG—Fault Event Upper Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIVC1REMAP
44-47h
00000000h
RO
32 bits
This register specifies the interrupt message address. For platforms supporting only
interrupt messages in the 32-bit address range, this register is treated as read-only
(0).
Bit
31:0
Access
RO
Default
Value
00000000h
RST/PWR
Description
Core
Message upper address (MUA): This register need to be
implemented only if hardware supports 64-bit message
address.
If implemented, the contents of this register specify the
upper 32-bits of a 64- bit MSI write transaction.
If hardware does not support 64-bit messages, the register
is treated as read-only (0).
NOTE: This field is reserved as this feature is not supported.
476
Datasheet