AC82G41SLGQ3 Datasheet, PDF (330/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
Bit
Access
Default
Value
RST/PWR
Description
Bus Master Enable (BME): This bit controls the HECI
host controller's ability to act as a system memory master
for data transfers. When this bit is cleared, HECI bus
master activity stops and any active DMA engines return to
an idle condition. This bit is made visible to firmware
through the H_PCI_CSR register, and changes to this bit
may be configured by the H_PCI_CSR register to generate
2
R/W
0b
Core
an ME MSI.
When this bit is 0, HECI is blocked from generating MSI to
the host processor.
Note that this bit does not block HECI accesses to ME-UMA
(i.e., writes or reads to the host and ME circular buffers
through the read window and write window registers still
cause ME backbone transactions to ME-UMA).
1
R/W
0b
Core
Memory Space Enable (MSE): This bit controls access to
the HECI host controller’s memory mapped register space.
0
RO
0b
Core
I/O Space Enable (IOSE): Not implemented, hardwired
to 0.
10.2.3
STS— Device Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
6-7h
0010h
RO
16 bits
Bit
15
14
13
12
11
10:9
8
7
6
5
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
0b
00b
0b
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Detected Parity Error (DPE): Not implemented,
hardwired to 0.
Signaled System Error (SSE): Not implemented,
hardwired to 0.
Received Master-Abort (RMA): Not implemented,
hardwired to 0.
Received Target Abort (RTA): Not implemented,
hardwired to 0.
Signaled Target-Abort (STA): Not implemented,
hardwired to 0.
DEVSEL# Timing (DEVT): These bits are hardwired to
00.
Master Data Parity Error Detected (DPD): Not
implemented, hardwired to 0.
Fast Back-to-Back Capable (FBC): Not implemented,
hardwired to 0.
Reserved
66 MHz Capable (C66): Not implemented, hardwired to
0.
330
Datasheet