AC82G41SLGQ3 Datasheet, PDF (80/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Register Description
4.4
Figure 9.
Routing Configuration Accesses
The (G)MCH supports two PCI related interfaces: DMI and PCI Express. The (G)MCH is
responsible for routing PCI and PCI Express configuration cycles to the appropriate
device that is an integrated part of the (G)MCH or to one of these two interfaces.
Configuration cycles to the ICH10/ICH7 internal devices and Primary PCI (including
downstream devices) are routed to the ICH10/ICH7 via DMI. Configuration cycles to
both the PCI Express Graphics PCI compatibility configuration space and the PCI
Express Graphics extended configuration space are routed to the PCI Express Graphics
port device or associated link.
MCH Configuration Cycle Flow Chart
DW I/O Write to
CONFIG_ADDRESS
with bit 31 = 1
I/O Read/Write to
CONFIG_DATA
MCH Generates
Type 1 Access
to PCI Express
Yes
Bus# = 0
No
Yes ^{Bus# > SEC BUS}
Bus# ≤ SUB BUS
in MCH Dev 1
No
Yes
Bus# =
SECONDARYBUS
in MCH Dev 1
No
MCH Generates
DMI Type 1
Configuration Cycle
Device# = 0 &
Function# = 0
Yes
MCH Claims
No
Device# = 1 &
Dev # 1 Enabled
Yes
& Function# = 0
No
MCH Generates
DMI Type 0
Configuration Cycle
MCH Claims
Device# = 0
No
MCH allows cycle to
go to DMI resulting
in Master Abort
Yes
MCH Generates
Type 0 Access
to PCI Express
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