AC82G41SLGQ3 Datasheet, PDF (104/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.20
Note:
PAM2—Programmable Attribute Map 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
92h
00h
RO, R/W/L
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C8000h–0CFFFFh.
All the bits in this register are locked in Intel TXT mode (82Q45/82Q43 GMCH only).
Bit
Access
Default
RST/
Value
PWR
Description
7:6
RO
00b
Core
Reserved
5:4
R/W/L
00b
Core
0CC000h-0CFFFFh Attribute (HIENABLE):
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are
serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are
serviced by DRAM.
3:2
RO
00b
Core
Reserved
1:0
R/W/L
00b
Core
0C8000h-0CBFFFh Attribute (LOENABLE): This field
controls the steering of read and write cycles that address
the BIOS area from 0C8000h to 0CBFFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are
serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are
serviced by DRAM.
104
Datasheet