AC82G41SLGQ3 Datasheet, PDF (362/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.6.1
IDEDATA—IDE Data Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
0h
00h
R/W
8 bits
The IDE data interface is a special interface that is implemented in the HW. This data
interface is mapped to IO space from the host and takes read and write cycles from the
host targeting master or slave device.
Writes from host to this register result in the data being written to ME memory.
Reads from host to this register result in the data being fetched from ME memory.
Data is typically written/ read in WORD's. ME-FW must enable hardware to allow it to
accept Host initiated Read/ Write cycles, else the cycles are dropped.
Bit
Access
Default
Value
RST/PWR
Description
IDE Data Register (IDEDR): Data Register implements
7:0
R/W
00h
Core
the data interface for IDE. All writes and reads to this
register translate into one or more corresponding write/
reads to ME memory
10.6.2
IDEERD1—IDE Error Register Device 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
1h
00h
R/W/V
8 bits
Reset: Host system reset or D3->D0 transition
This register implements the Error register of the command block of the IDE function.
This register is read only by the HOST interface when DEV = 1 (slave device).
When the HOST writes the same address it writes to the Features register.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Error Data (IDEED): Drive reflects its error/
diagnostic code to the host via this register at different
times.
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Datasheet