AC82G41SLGQ3 Datasheet, PDF (491/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
Access
47:40
RO
39
RO
38
RO
37:34
RO
33:24
RO
23
RO
Default
Value
00h
0b
0b
0h
020h
0h
RST/PWR
Description
Core
Core
Number of Faultrecording Registers (NFR): This field
indicates a value of N-1, where N is the number of fault
recording registers supported by hardware.
Implementations must support at least one fault recording
register (NFR = 0) for each DMAremapping hardware unit
in the platform.
The maximum number of fault recording registers per
DMA-remapping hardware unit is 256.
Page-Selective Invalidation Support (PSI):
0 = Hardware does not support page-selective IOTLB
invalidations.
1 = Hardware supports page-selective IOTLB invalidations.
The MAMV field indicates the maximum number of
contiguous translations that may be invalidated in a
single request.
Core
Core
Core
Core
NOTE: This field is reserved as this feature is not
supported.
Reserved
Super-Page support (SPS): This field indicates the super
page sizes supported by hardware.
A value of 1 in any of these bits indicates the
corresponding super-page size is supported. The super-
page sizes corresponding to various bit positions within this
field are:
0 = 21-bit offset to page frame
1 = 30-bit offset to page frame
2 = 39-bit offset to page frame
3 = 48-bit offset to page frame
Fault-recording Register offset (FRO): This field
specifies the location to the first fault recording register
relative to the register base address of this DMA-
remapping hardware unit.
If the register base address is X, and the value reported in
this field is Y, the address for the first fault recording
register is calculated as X+(16*Y).
Isochrony (ISOCH):
0 = Remapping hardware unit has no critical isochronous
requesters in its scope.
1 = Remapping hardware unit has one or more critical
isochronous requesters in its scope. To ensure
isochronous performance, software must ensure
invalidation operations do not impact active DMA
streams from such requesters. This implies, when
isochronous DMA is active, software performs page
selective invalidations (and not coarser invalidations)
NOTE: This field is reserved as this feature is not
supported.
Datasheet
491