AC82G41SLGQ3 Datasheet, PDF (466/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
23
22:0
Access
RO
RO
Default
Value
0b
000000h
RST/PWR
Description
Core
Core
Compatibility Format Interrupt (CFI): This field is valid
only for Intel®64 implementations supporting interrupt-
remapping. Software writes to this field to enable or
disable Compatibility Format interrupts on Intel®64
platforms. The value in this field is effective only when
interrupt-remapping is enabled and Legacy Interrupt Mode
is active.
0 = Block Compatibility format interrupts.
1 = Process Compatibility format interrupts as pass-
through (bypass interrupt remapping).
Hardware reports the status of updating this field through
the CFIS field in the Global Status register.
Refer to Section 5.4.1 for details on Compatibility Format
interrupt requests.
The value returned on a read of this field is undefined.
NOTE: This field is not implemented on Itanium™
implementations.
NOTE: This field is reserved as this feature is not
supported.
Reserved
12.2.5
GSTS_REG—Global Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIVC1REMAP
1C-1Fh
00000000h
RO
32 bits
This register reports general DMA-remapping hardware status.
Bit
Access
Default
Value
RST/PWR
Description
31
RO
30
RO
Translation Enable Status (TES): This field indicates the
status of DMA-remapping hardware.
0b
Core
0 = DMA-remapping hardware is not enabled
1 = DMA-remapping hardware is enabled
Root Table Pointer Status (RTPS): This field indicates
the status of the root- table pointer in hardware.
This field is cleared by hardware when software sets the
0b
Core
SRTP field in the Global Command register. This field is set
by hardware when hardware completes the set root-table
pointer operation using the value provided in the Root-
Entry Table Address register.
466
Datasheet