AC82G41SLGQ3 Datasheet, PDF (452/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.1.18 PHMLIMIT_REG—Protected High-Memory Limit Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/VC0PREMAP
78-7Fh
0000000000000000h
R/W, RO
64 bits
This register is used to setup the limit address of DMA protected high-memory region.
This register must be setup before enabling protected memory through PMEN_REG,
and must not be updated when protected memory regions are enabled. When
LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO). When
LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated as R/W).
This register is always treated as RO for implementations not supporting protected high
memory region (PHMR field reported as 0 in the Capability register). The alignment of
the protected high memory region limit depends on the number of reserved bits (N) of
this register. Software may determine the value of N by writing all 1s to this register,
and finding most significant zero bit position below host address width (HAW) in the
value read back from the register. Bits N:0 of the limit register is decoded by hardware
as all 1s. The protected high-memory base and limit registers functions as follows.
• Programming the protected low-memory base and limit registers with the same
value in bits HAW:(N+1) specifies a protected low-memory region of size 2(N+1)
bytes.
• Programming the protected high-memory limit register with a value less than the
protected high-memory base register disables the protected high-memory region.
Bit
63:21
20:0
Access
R/W
RO
Default
Value
000000000
00h
000000h
RST/PWR
Description
Core
Core
Protected High-Memory Limit (PHML): This register
specifies the last host physical address of the DMA
protected high-memory region in system memory.
Hardware may not use bits 63:HAW, where HAW is the host
address width.
Reserved
452
Datasheet