AC82G41SLGQ3 Datasheet, PDF (338/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.2.19 MID— Message Signaled Interrupt Identifiers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
8C-8Dh
0005h
RO
16 bits
Bit
15:8
7:0
Access
RO
RO
Default
Value
00h
05h
RST/PWR
Description
Core
Core
Next Pointer (NEXT): This field indicates the next item in
the list. This can be other capability pointers (such as PCI-
X or PCI-Express) or it can be the last item in the list.
Capability ID (CID): Capabilities ID indicates MSI.
10.2.20 MC— Message Signaled Interrupt Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
8E-8Fh
0080h
R/W, RO
16 bits
Bit
15:8
7
6:4
3:1
0
Access
RO
RO
RO
RO
R/W
Default
Value
00h
1b
000b
000b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Reserved
64 Bit Address Capable (C64): Specifies whether
capable of generating 64-bit messages.
Multiple Message Enable (MME): Not implemented,
hardwired to 0.
Multiple Message Capable (MMC): Not implemented,
hardwired to 0.
MSI Enable (MSIE): If set, MSI is enabled and traditional
interrupt pins are not used to generate interrupts.
10.2.21 MA— Message Signaled Interrupt Message Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
90-93h
00000000h
R/W, RO
32 bits
Bit
31:2
1:0
Access
R/W
RO
Default
Value
00000000h
00b
RST/PWR
Description
Core
Core
Address (ADDR): Lower 32 bits of the system specified
message address, always DW aligned.
Reserved
338
Datasheet