AC82G41SLGQ3 Datasheet, PDF (204/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.39
LCTL—Link Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
B0-B1h
0000h
R/W, RO, R/W/SC
16 bits
This register allows control of PCI Express link.
Bit
15:12
Access
RO
11
R/W
10
R/W
9
RO
8
RO
7
R/W
Default
Value
0000b
0b
0b
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Reserved
Link Autonomous Bandwidth Interrupt Enable
(LABIE): When Set, this bit enables the generation of an
interrupt to indicate that the Link Autonomous Bandwidth
Status bit has been Set.
This bit is not applicable and is reserved for Endpoint
devices, PCI Express to PCI/PCI-X bridges, and Upstream
Ports of Switches.
Devices that do not implement the Link Bandwidth
Notification capability must hardwire this bit to 0b.
Link Bandwidth Management Interrupt Enable
(LBMIE): When Set, this bit enables the generation of an
interrupt to indicate that the Link Bandwidth Management
Status bit has been Set.
This bit is not applicable and is reserved for Endpoint
devices, PCI Express to PCI/PCI-X bridges, and Upstream
Ports of Switches.
Hardware Autonomous Width Disable (HAWD): When
Set, this bit disables hardware from changing the Link
width for reasons other than attempting to correct
unreliable Link operation by reducing Link width.
Devices that do not implement the ability autonomously to
change Link width are permitted to hardwire this bit to 0b.
Enable Clock Power Management (ECPM): Applicable
only for form factors that support a "Clock Request"
(CLKREQ#) mechanism, this enable functions as follows:
0 = Clock power management is disabled and device must
hold CLKREQ# signal low
1 = When this bit is set to 1, the device is permitted to use
CLKREQ# signal to power manage link clock according
to protocol defined in appropriate form factor
specification.
Components that do not support Clock Power Management
(as indicated by a 0b value in the Clock Power
Management bit of the Link Capabilities Register) must
hardwire this bit to 0b.
Reserved
204
Datasheet