AC82G41SLGQ3 Datasheet, PDF (205/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
Bit
Access
Default
Value
RST/PWR
Description
6
R/W
0b
5
R/W/SC
0b
4
R/W
0b
3
RO
0b
2
RO
0b
1:0
R/W
00b
Core
Core
Core
Core
Core
Core
Common Clock Configuration (CCC):
0 = Indicates that this component and the component at
the opposite end of this Link are operating with
asynchronous reference clock.
1 = Indicates that this component and the component at
the opposite end of this Link are operating with a
distributed common reference clock.
The state of this bit affects the N_FTS value advertised
during link training.
See PEGL0SLAT at offset 22Ch.
Retrain Link (RL):
0 = Normal operation.
1 = Full Link retraining is initiated by directing the Physical
Layer LTSSM from L0 or L1 states to the Recovery
state.
This bit always returns 0 when read. This bit is cleared
automatically (no need to write a 0).
Link Disable (LD):
0 = Normal operation
1 = Link is disabled. Forces the LTSSM to transition to the
Disabled state (via Recovery) from L0 or L1 states.
Link retraining happens automatically on 0 to 1
transition, just like when coming out of reset.
Writes to this bit are immediately reflected in the value
read from the bit, regardless of actual Link state.
Read Completion Boundary (RCB): Hardwired to 0 to
indicate 64 byte.
Reserved
Active State PM (ASPM): This field controls the level of
active state power management supported on the given
link.
00 = Disabled
01 = Reserved
10 = L1 Entry Enabled
11 = L1 Entry Enabled
Datasheet
205