AC82G41SLGQ3 Datasheet, PDF (420/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Trusted Execution Technology Registers (Intel^® 82Q45 and 82Q43 GMCH Only)
11.1.19 TXT.DPR—DMA Protected Range
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/TXT Specific
330-337h
0000000000000000h
RO, RW/L, RWO
64 bits
DMA protected range register.
Bit
63:32
31:20
19:12
Access
RO
RO
RO
Default
Value
Description
00000000h Reserved
000h
Top of DPR (TopOfDPR): Top address + 1 of DPR. This is the base of TSEG.
Bits 19:0 of the BASE reported here are 0x0_0000.
00h
Reserved
DMA Protected Memory Size (DPR.SIZE): This is the size of memory, in
MB, that will be protected from DMA accesses. A value of 0x00 in this field
means no additional memory is protected. The maximum amount of memory
that will be protected is 255 MB.
The amount of memory reported in this field will be protected from all DMA
accesses, including translated CPU accesses and graphics. The top of the
protected range is the BASE of TSEG–1.
11:4
RW/L
3:1
RO
0
RWO
00h
000b
0b
NOTE: If TSEG is not enabled, then the top of this range becomes the base
of stolen graphics, or ME stolen space or TOLUD, whichever would
have been the location of TSEG, assuming it had been enabled.
The DPR range works independently of any other range, including the PMRC
checks in VTd, and is done post any VTd translation. Therefore, incoming
cycles are checked against this range after the VTd translation and faulted if
they hit this protected range, even if they passed the VTd translation.
All the memory checks are OR'ed with respect to NOT being allowed to go to
memory. So if either PMRC, DPR OR a VTd translation disallows the cycle,
then the cycle is not allowed to go to memory. Or in other words, all the
above checks must pass before a cycle is allowed to DRAM.
Reserved
LOCK (LOCK): Bits 19:0 are locked down in this register when this bit is set.
11.1.20 TXT.CMD.OPEN.LOCALITY1—TXT Open Locality 1
Command
This command will open Locality1 for decode as an TXT space by the chipset. If the
locality is closed, then cycles to the locality 1 address range are not decoded as TXT
cycles.
Note:
PRIVATE space must also be Open for Locality 1 to be decoded as TXT Space.
420
Datasheet