AC82G41SLGQ3 Datasheet, PDF (135/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.12
C0CYCTRKREFR—Channel 0 CYCTRK REFR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
25B-25Ch
0000h
RO, R/W
16 bits
This register is for Channel 0 CYCTRK Refresh.
Bit
15:13
12:9
8:0
Access
RO
R/W
R/W
Default
Value
RST/PWR
Description
000b
0000b
000000000b
Core
Core
Core
Reserved
Same Rank PALL to REF Delayed
(C0sd_cr_pchgall_rfsh): This configuration register
indicates the minimum allowed spacing (in DRAM clocks)
between the PRE-ALL and REF commands to the same
rank.
Same Rank REF to REF Delayed (C0sd_cr_rfsh_rfsh):
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two REF commands to
same ranks.
5.2.13
C0CKECTRL—Channel 0 CKE Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
260-263h
00000800h
R/W, RO
32 bits
Bit
31:28
27
Access
RO
R/W
26:24
R/W
23
R/W
22
R/W
Default
Value
0000b
0b
000b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Reserved
start the self-refresh exit sequence
(sd0_cr_srcstart): This configuration register indicates
the request to start the self-refresh exit sequence
CKE pulse width requirement in high phase
(sd0_cr_cke_pw_hl_safe): This configuration register
indicates CKE pulse width requirement in high phase. This
field corresponds to tCKE (high) in the DDR Specification.
Rank 3 Population (sd0_cr_rankpop3):
1 = Rank 3 populated
0 = Rank 3 not populated This register is locked by ME
stolen Memory lock.
Rank 2 Population (sd0_cr_rankpop2):
1 = Rank 2 populated
0 = Rank 2 not populated
This register is locked by ME stolen Memory lock.
Datasheet
135