AC82G41SLGQ3 Datasheet, PDF (417/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Trusted Execution Technology Registers (Intel^® 82Q45 and 82Q43 GMCH Only)
11.1.11 TXT.SINIT.MEMORY.SIZE—TXT SINIT Memory Size
Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/TXT Specific
278-27Fh
0000000000000000h
RW
64 bits
This register contains the size in bytes of the memory region set aside by the BIOS for
loading an SINIT AC module. This register is initialized by the BIOS. The system
software may read this register when loading an SINIT module.
Bit
63:0
Access
Default
Value
Description
TXT.SINIT.SIZE (TXT.SINIT.SIZE): Base address of the SINIT code.
Hardware does not use the information contained in this register. It is used as
a mailbox between two pieces of software.
RW
0000000000
000000h
Note: Bits 11:0 are not implemented because the SINIT code must be aligned
to a 4K page boundary.
Systems supporting a 36 bit address space may make bits 63:36 as RO with
reads returning '0'.
11.1.12 TXT.MLE.JOIN—TXT MLE Join Base Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/TXT Specific
290-297h
0000000000000000h
RW, RO
64 bits
Holds a physical address pointer to the base of the join data structure referenced by
RLPs in response to a GETSEC[WAKEUP] while operating between SENTER and SEXIT.
Bit
63:36
35:0
Access
RO
RW
Default
Value
Description
0000000h
TXT MLE Join Base (Reserved) (TXT.MLE.JOIN_R): Base address of the
MLE join code.
For chipsets that only support 64GB FSB addressing (36b addressing), bits
63:36 may be RO – reserved(0)
TXT MLE Join Base (TXT.MLE.JOIN): Base address of the MLE join code.
00000000
0h
For chipsets that only support 64 GB FSB addressing (36b addressing), bits
63:36 may be RO – reserved(0)
Datasheet
417