AC82G41SLGQ3 Datasheet, PDF (11/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

10.3
10.4
10.5
10.6
10.2.18PMCS— PCI Power Management Control And Status .................................. 337
10.2.19MID— Message Signaled Interrupt Identifiers ........................................... 338
10.2.20MC— Message Signaled Interrupt Message Control.................................... 338
10.2.21MA— Message Signaled Interrupt Message Address................................... 338
10.2.22MUA— Message Signaled Interrupt Upper Address (Optional) ..................... 339
10.2.23MD— Message Signaled Interrupt Message Data ....................................... 339
10.2.24HIDM—HECI Interrupt Delivery Mode ...................................................... 339
HECI PCI MMIO Space Registers ........................................................................ 340
10.3.1 H_CB_WW— Host Circular Buffer Write Window........................................ 340
10.3.2 H_CSR— Host Control Status ................................................................. 341
10.3.3 ME_CB_RW— ME Circular Buffer Read Window ......................................... 342
10.3.4 ME_CSR_HA— ME Control Status Host Access .......................................... 343
Second HECI Function MMIO Space Registers ...................................................... 344
10.4.1 H_CB_WW— Host Circular Buffer Write Window........................................ 344
10.4.2 H_CSR— Host Control Status ................................................................. 345
10.4.3 ME_CB_RW— ME Circular Buffer Read Window ......................................... 346
10.4.4 ME_CSR_HA— ME Control Status Host Access .......................................... 347
IDE Function for Remote Boot and Installations PT IDER Registers ......................... 348
10.5.1 ID—Identification ................................................................................. 349
10.5.2 CMD—Command Register ...................................................................... 349
10.5.3 STS—Device Status .............................................................................. 350
10.5.4 RID—Revision ID.................................................................................. 351
10.5.5 CC—Class Codes .................................................................................. 351
10.5.6 CLS—Cache Line Size............................................................................ 351
10.5.7 MLT—Master Latency Timer ................................................................... 352
10.5.8 PCMDBA—Primary Command Block IO Bar ............................................... 352
10.5.9 PCTLBA—Primary Control Block Base Address .......................................... 353
10.5.10SCMDBA—Secondary Command Block Base Address ................................. 353
10.5.11SCTLBA—Secondary Control Block base Address....................................... 354
10.5.12LBAR—Legacy Bus Master Base Address .................................................. 354
10.5.13SS—Sub System Identifiers ................................................................... 355
10.5.14EROM—Expansion ROM Base Address...................................................... 355
10.5.15CAP—Capabilities Pointer....................................................................... 355
10.5.16INTR—Interrupt Information .................................................................. 356
10.5.17MGNT—Minimum Grant ......................................................................... 356
10.5.18MLAT—Maximum Latency ...................................................................... 356
10.5.19PID—PCI Power Management Capability ID .............................................. 357
10.5.20PC—PCI Power Management Capabilities ................................................. 357
10.5.21PMCS—PCI Power Management Control and Status ................................... 358
10.5.22MID—Message Signaled Interrupt Capability ID ........................................ 359
10.5.23MC—Message Signaled Interrupt Message Control..................................... 359
10.5.24MA—Message Signaled Interrupt Message Address.................................... 360
10.5.25MAU—Message Signaled Interrupt Message Upper Address ........................ 360
10.5.26MD—Message Signaled Interrupt Message Data ........................................ 360
IDE BAR0 ....................................................................................................... 361
10.6.1 IDEDATA—IDE Data Register ................................................................. 362
10.6.2 IDEERD1—IDE Error Register Device 1 .................................................... 362
10.6.3 IDEERD0—IDE Error Register DEV0 ........................................................ 363
10.6.4 IDEFR—IDE Features Register ................................................................ 363
10.6.5 IDESCIR—IDE Sector Count In Register................................................... 364
10.6.6 IDESCOR1—IDE Sector Count Out Register Dev1...................................... 364
10.6.7 IDESCOR0—IDE Sector Count Out Register Device 0 ................................. 365
10.6.8 IDESNOR0—IDE Sector Number Out Register Device 0 .............................. 365
10.6.9 IDESNOR1—IDE Sector Number Out Register Device 1 .............................. 366
10.6.10IDESNIR—IDE Sector Number In Register................................................ 366
Datasheet
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