AC82G41SLGQ3 Datasheet, PDF (548/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Functional Description
13.9
13.9.1
Thermal Sensor
There are several registers that need to be configured to support the (G)MCH thermal
sensor functionality and SMI# generation. Customers must enable the Catastrophic
Trip Point as protection for the (G)MCH. If the Catastrophic Trip Point is crossed, then
the (G)MCH will instantly turn off all clocks inside the device. Customers may
optionally enable the Hot Trip Point to generate SMI#. Customers will be required to
then write their own SMI# handler in BIOS that will speed up the (G)MCH (or system)
fan to cool the part.
PCI Device 0, Function 0
The SMICMD register requires that a bit be set to generate an SMI# when the Hot Trip
point is crossed. The ERRSTS register can be inspected for the SMI alert.
Address
C8–C9h
CC–CDh
Register
Symbol
ERRSTS
SMICMD
Register Name
Error Status
SMI Command
Default Value
0000h
0000h
Access
RWC/S, RO
RO, R/W
13.9.2
GMCHBAR Thermal Sensor Registers
The Digital Thermometer Configuration Registers reside in the MCHBAR configuration
space.
Address
CD8–CD8h
CD9–CD9h
CDA–CDAh
CDC–CDFh
CE2–CE2h
CE4–CE4h
CE6–CE6h
CEA–CEBh
CF1–CF1h
Register
Symbol
TSC1
TSC2
TSS
TSTTP
TCO
THERM1
THERM3
TIS
TSMICMD
Register Name
Thermal Sensor Control 1
Thermal Sensor Control 2
Thermal Sensor Status
Thermal Sensor Temperature Trip
Point
Thermal Calibration Offset
Hardware Throttle Control
TCO Fuses
Thermal Interrupt Status
Thermal SMI Command
Default Value
00h
00h
00h
00000000h
00h
00h
00h
0000h
00h
Access
RW/L, R/W,
RS/WC
RO, RW/L
RO
RO, RW, R/W/L
RW/L/K, R/W/L
RW/L, RO,
R/W/L/K
RO, RS/WC
RO, R/WC
RO, R/W
548
Datasheet