AC82G41SLGQ3 Datasheet, PDF (77/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Register Description
4.2
4.2.1
Item
R/W/SC/L
R/WO
W
Definition
Read / Write / Self Clear / Lockable bit(s). These bits can be read and written
by software. When the bit is ‘1’, hardware may clear the bit to ‘0’ based upon
internal events, possibly sooner than any subsequent software read could
retrieve a ‘1’. Additionally there is a bit (which is marked R/W/K or R/W/L/K)
that, when set, prohibits this bit field from being writeable (bit field becomes
Read Only).
Write Once bit(s). Once written by software, bits with this attribute become
Read Only. These bits can only be cleared by a Reset. If there are multiple
R/WO fields within a DWord, they should be written all at once (atomically) to
avoid capturing an incorrect value.
Write Only. These bits may be written by software, but will always return zeros
when read. They are used for write side-effects. Any data written to these
registers cannot be retrieved.
Configuration Process and Registers
Platform Configuration Structure
The DMI physically connects the (G)MCH and the Intel ICH10/ICH7; so, from a
configuration standpoint, the DMI is logically PCI bus 0. As a result, all devices internal
to the (G)MCH and the Intel ICH10/ICH7 appear to be on PCI bus 0.
The ICH10/ICH7 internal LAN controller does not appear on bus 0 – it appears on the
external PCI bus (whose number is configurable).
The system’s primary PCI expansion bus is physically attached to the Intel ICH10/ICH7
and, from a configuration perspective, appears to be a hierarchical PCI bus behind a
PCI-to-PCI bridge and therefore has a programmable PCI Bus number. The PCI Express
Graphics Attach appears to system software to be a real PCI bus behind a PCI-to-PCI
bridge that is a device resident on PCI bus 0.
A physical PCI bus 0 does not exist and that DMI and the internal devices in the
(G)MCH and Intel ICH10/ICH7 logically constitute PCI Bus 0 to configuration software.
This is shown in the following figure.
The (G)MCH contains the following PCI devices within a single physical component. The
configuration registers for the four devices are mapped as devices residing on PCI bus
0.
• Device 0: Host Bridge/DRAM Controller. Logically this appears as a PCI device
residing on PCI bus 0. Device 0 contains the standard PCI header registers, PCI
Express base address register, DRAM control (including thermal/throttling control),
configuration for the DMI, and other (G)MCH specific registers.
• Device 1: Host-PCI Express Bridge. Logically this appears as a “virtual” PCI-to-
PCI bridge residing on PCI bus 0 and is compliant with PCI Express Specification
Revision 1.0. Device 1 contains the standard PCI-to-PCI bridge registers and the
standard PCI Express/PCI configuration registers (including the PCI Express
memory address mapping). It also contains Isochronous and Virtual Channel
controls in the PCI Express extended configuration space.
• Device 2: Internal Graphics Control (82Q45, 82Q43, 82B43, 82G45, 82G43,
82G41 GMCH only). Logically, this appears as a PCI device residing on PCI bus
#0. Physically, device 2 contains the configuration registers for 3D, 2D, and display
functions.
• Device 3: Management Engine Control. ME control.
Datasheet
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