AC82G41SLGQ3 Datasheet, PDF (475/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.2.10 FEDATA_REG—Fault Event Data Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIVC1REMAP
3C-3Fh
00000000h
RO, R/W
32 bits
This register specifies the interrupt message data
Bit
Access
31:16
RO
15:0
R/W
Default
Value
0000h
0000h
RST/PWR
Description
Core
Core
Extended Interrupt Message Data (EIMD): This field is
valid only for implementations supporting 32-bit MSI data
fields.Hardware implementations supporting only 16-bit
MSI data may treat this field as read only (0).
Interrupt message data (IMD): Data value in the fault-
event interrupt message.
12.2.11 FEADDR_REG—Fault Event Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIVC1REMAP
40-43h
00000000h
R/W, RO
32 bits
This register specifies the interrupt message address.
Bit
31:2
1:0
Access
R/W
RO
Default
Value
00000000h
0h
RST/PWR
Description
Core
Core
Message address (MA): When fault events are enabled,
the contents of this register specify the DWord aligned
address (bits 31:2) for the MSI memory write transaction.
Reserved
Datasheet
475