AC82G41SLGQ3 Datasheet, PDF (293/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.1.27
MC—Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
92-93h
0000h
RO, R/W
16 bits
System software can modify bits in this register, but the device is prohibited from doing
so. If the device writes the same message multiple times, only one of those messages
is assured to be serviced. If all of them must be serviced, the device must not generate
the same message again until the driver services the earlier one.
Bit
15:8
7
6:4
3:1
0
Access
RO
RO
R/W
RO
R/W
Default
Value
00h
0b
000b
000b
0b
RST/PWR
Description
Core
Core
FLR, Core
Core
FLR, Core
Reserved
64 Bit Capable (64BCAP): Hardwired to 0 to indicate
that the function does not implement the upper 32 bits of
the Message address register and is incapable of
generating a 64-bit memory address.
This may need to change in future implementations when
addressable system memory exceeds the 32b/4 GB limit.
Multiple Message Enable (MME): System software
programs this field to indicate the actual number of
messages allocated to this device. This number will be
equal to or less than the number actually requested.
The encoding is the same as for the MMC field below.
Multiple Message Capable (MMC): System Software
reads this field to determine the number of messages
being requested by this device.
000 = 1
All other encodings are reserved.
MSI Enable (MSIEN): This bit controls the ability of this
device to generate MSIs.
9.1.28
MA—Message Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
94-97h
00000000h
R/W, RO
32 bits
Bit
31:2
1:0
Access
R/W
RO
Default
Value
00000000h
00b
RST/PWR
Description
FLR, Core
Core
Message Address (MESSADD): This field is used by
system software to assign an MSI address to the device.
The device handles an MSI by writing the padded contents
of the MD register to this address.
Force DWord Align (FDWORD): Hardwired to 0 so that
addresses assigned by system software are always aligned
on a DWord address boundary.
Datasheet
293