AC82G41SLGQ3 Datasheet, PDF (231/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
Table 14.
Host-Secondary PCI Express* Bridge Register Address Map (D6:F0) (Sheet 3
of 3)
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
100–103h
104–107h
108–10Bh
10C–10Dh
110–113h
114–117h
11A–11Bh
140–143h
144–147h
150–153h
158–15Fh
VCECH
PVCCAP1
PVCCAP2
PVCCTL
VC0RCAP
VC0RCTL
VC0RSTS
RCLDECH
ESD
LE1D
LE1A
Virtual Channel Enhanced Capability
Header
Port VC Capability Register 1
Port VC Capability Register 2
Port VC Control
VC0 Resource Capability
VC0 Resource Control
VC0 Resource Status
Root Complex Link Declaration Enhanced
Element Self Description
Link Entry 1 Description
Link Entry 1 Address
14010002h
RO
00000000h
00000000h
0000h
00000000h
800000FFh
0002h
00010005h
03000100h
00000000h
0000000000
000000h
RO
RO
RO, RW
RO
RO, RW
RO
RO
RO, RWO
RO, RWO
RO, RWO
8.1
VID1—Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
0–1h
8086h
RO
16 bits
This register combined with the Device Identification register uniquely identify any PCI
device.
Bit
15:0
Access
RO
Default
Value
8086h
RST/
PWR
Core
Description
Vendor Identification (VID1): PCI standard identification for Intel.
Datasheet
231