AC82G41SLGQ3 Datasheet, PDF (353/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.5.9
PCTLBA—Primary Control Block Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
14-17h
00000001h
RO, R/W
32 bits
Reset: Host system Reset or D3->D0 transition of the function
This 4-byte I/O space is used in Native Mode for the Primary Controller's Control Block
ie BAR1
Bit
31:16
15:2
1
0
Access
RO
R/W
RO
RO
Default
Value
0000h
0000h
0b
1b
RST/PWR
Description
Core
Core
Core
Core
Reserved
Base Address (BAR): Base Address of the BAR1 I/O
space (4 consecutive I/O locations)
Reserved
Resource Type Indicator (RTE): This bit indicates a
request for I/O space
10.5.10 SCMDBA—Secondary Command Block Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
18-1Bh
00000001h
RO, R/W
32 bits
Reset: Host System Reset or D3->D0 transition of the function
This 8-byte I/O space is used in Native Mode for the secondary Controller's Command
Block. Secondary Channel is not implemented and reads return 7F7F7F7Fh and all
writes are ignored.
Bit
31:16
15:3
2:1
0
Access
RO
R/W
RO
RO
Default
Value
0000h
0000h
00b
1b
RST/PWR
Description
Core
Core
Core
Core
Reserved
Base Address (BAR): Base Address of the I/O space (8
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE): This bit indicates a
request for I/O space.
Datasheet
353