AC82G41SLGQ3 Datasheet, PDF (179/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
Bit
4
3
2:0
6.1.5
Access
RO
RO
RO
Default
Value
1b
0b
000b
RST/PWR
Description
Core
Core
Core
Capabilities List (CAPL): This bit indicates that a
capabilities list is present. Hardwired to 1.
INTA Status (INTAS): This bit indicates that an interrupt
message is pending internally to the device. Only PME and
Hot Plug sources feed into this status bit (not PCI INTA-
INTD assert and de-assert messages). The INTA Assertion
Disable bit, PCICMD1[10], has no effect on this bit.
Note that INTA emulation interrupts received across the
link are not reflected in this bit.
Reserved
RID1—Revision Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
8h
see description below
RO
8 bits
This register contains the revision number of the (G)MCH device 1. These bits are read
only and writes to this register have no effect.
Bit
Access
Default
Value
RST/PWR
Description
Revision Identification Number (RID1): This is an 8-
7:0
RO
see
description
Core
bit value that indicates the revision identification number
for the (G)MCH Device 0. Refer to the Intel^® 4 Series
Chipset Family Specification Update for the value of this
register.
Datasheet
179