AC82G41SLGQ3 Datasheet, PDF (248/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
Bit
Access
Default
Value
RST/
PWR
Description
1
RW
0
RW
SERR Enable (SERREN):
0 = No forwarding of error messages from secondary side to primary side
0b
Core
that could result in an SERR.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR
message when individually enabled by the Root Control register.
Parity Error Response Enable (PEREN): Controls whether or not the
Master Data Parity Error bit in the Secondary Status register is set when
the MCH receives across the link (upstream) a Read Data Completion
0b
Core ^{Poisoned Transaction Layer Packet.}
0 = Master Data Parity Error bit in Secondary Status register can NOT be
set.
1 = Master Data Parity Error bit in Secondary Status register CAN be set.
8.25 PM_CAPID1—Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
80–83h
C8039001h
RO
32 bits
Bit
Access
Default
Value
RST/
PWR
Description
31:27 RO
26
RO
25
RO
24:22 RO
21
RO
20
RO
19
RO
18:16 RO
15:8 RO
7:0
RO
19h
0b
0b
000b
0b
0b
0b
011b
90h
01h
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
PME Support (PMES): This field indicates the power states in which this
device may indicate PME wake via PCI Express messaging. D0, D3hot &
D3cold. This device is not required to do anything to support D3hot and
D3cold, it simply must report that those states are supported. Refer to the
PCI Power Management 1.1 specification for encoding explanation and
other power management details.
D2 Power State Support (D2PSS): Hardwired to 0 to indicate that the
D2 power management state is NOT supported.
D1 Power State Support (D1PSS): Hardwired to 0 to indicate that the
D1 power management state is NOT supported.
Auxiliary Current (AUXC): Hardwired to 0 to indicate that there are no
3.3Vaux auxiliary current requirements.
Device Specific Initialization (DSI): Hardwired to 0 to indicate that
special initialization of this device is NOT required before generic class
device driver is to use it.
Auxiliary Power Source (APS): Hardwired to 0.
PME Clock (PMECLK): Hardwired to 0 to indicate this device does NOT
support PMEB generation.
PCI PM CAP Version (PCIPMCV): A value of 011b indicates that this
function complies with PCI Power Management Interface Specification,
Revision 1.2.
Pointer to Next Capability (PNC): This contains a pointer to the next
item in the capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then the next
item in the capabilities list is the Message Signaled Interrupts (MSI)
capability at 90h.
Capability ID (CID): Value of 01h identifies this linked list item
(capability structure) as being for PCI Power Management registers.
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Datasheet