AC82G41SLGQ3 Datasheet, PDF (415/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Trusted Execution Technology Registers (Intel^® 82Q45 and 82Q43 GMCH Only)
11.1.5
TXT.ERRORCODE (AKA TXT.CRASH)—TXT Error Code
Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/TXT Specific
30-33h
00000000h
RW
32 bits
When software discovers an error, it can write this scratchpad register. The register is
NOT reset by a standard reset, and thus allows diagnostic software (after the reset) to
determine why the SENTER sequence failed (by examining various status bits). All
defined bits in this register are sticky across soft reboot.
Bit Access Default Value
Description
31:0 RWC
00000000h
Error Code (CRASH): Default 0 on power-up. Otherwise, previous value
on reset.
11.1.6
11.1.7
TXT.CMD.RESET—TXT System Reset Command
When this command is invoked, the chipset resets the entire platform. Hardware
naturally delays the assertion of reset sufficiently such that any previous writes to
ERRORCODE register should have completed. If software wants to guarantee that it is
not reliant upon this race, it must read back the ERRORCODE register before writing
the System Reset Command.
TXT.CMD.CLOSE-PRIVATE—TXT Close Private Command
The processor that authenticates the SEXIT code does this to prevent the TXT Private
address space from being accessed using standard memory read/write cycles.
System Software (i.e. MLE - Measured Launched Environment) is required to fence
after this command is performed. This can be achieved by reading back the STS flag to
see that it is no longer set after performing the CLOSE-PRIVATE command.
Datasheet
415