AC82G41SLGQ3 Datasheet, PDF (490/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.3.1
VER_REG—Version Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/GFXVTBAR
0-3h
00000010h
RO
32 bits
This register reports the architecture version supported. Backward compatibility for the
architecture is maintained with new revision numbers, allowing software to load DMA-
remapping drivers written for prior architecture versions.
Bit
31:8
7:4
3:0
Access
RO
RO
RO
Default
Value
000000h
1h
0h
RST/PWR
Description
Core
Core
Core
Reserved
Major Version number (MAX): This field indicates
supported architecture version.
Minor Version number (MIN): This field indicates
supported architecture minor version.
12.3.2
CAP_REG—Capability Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/GFXVTBAR
8-Fh
00C0000020630272h
RO
64 bits
This register reports general translation hardware capabilities.
Bit
63:56
Access
RO
55
RO
54
RO
53:48
RO
Default
Value
00h
1h
1h
00h
RST/PWR
Description
Core
Core
Core
Core
Reserved
DMA Read Draining (DRD):
0 = As part of IOTLB invalidations, hardware does not
support draining of translated DMA read requests
queued within the root complex
1 = As part of IOTLB invalidations, hardware supports
draining of translated DMA read requests queued
within the root complex
DMA Write Draining (DWD):
0 = On IOTLB invalidations, hardware does not support
draining of translated DMA writes queued within the
root complex.
0 = On IOTLB invalidations, hardware supports draining of
translated DMA writes queued within the root complex.
Maximum Address Mask Value (MAMV): The value in
this field indicates the maximum supported value for the
Address Mask (AM) field in the Invalidation Address
(IVA_REG) register.
NOTE: This field is reserved as this feature is not
supported.
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