AC82G41SLGQ3 Datasheet, PDF (410/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Trusted Execution Technology Registers (Intel^® 82Q45 and 82Q43 GMCH Only)
Address
Offset
Symbol
Register Name
318–31Fh TXT.MSEG.SIZE TXT MSEG Size Address Register
320–327h TXT.SCRATCHPAD.0 TXT Scratch Pad 0 Register
328–32Fh TXT.SCRATCHPAD.1 TXT Scratch Pad 1 Register
330–337h
TXT.DPR
DMA Protected Range
380–387h
TXT.CMD.OPEN.LOC
ALITY1
TXT Open Locality 1 Command
388–38Fh
TXT.CMD.CLOSE.LO
CALITY1
TXT Close Locality 1 Command
390–397h
TXT.CMD.OPEN.LOC
ALITY2
TXT Open Locality 2 Command
398–39Fh
TXT.CMD.CLOSE.LO
CALITY2
TXT Close Locality 2 Command
400–41Fh TXT.PUBLIC.KEY TXT Chipset Public Key Hash
8E0–8E7h TXT.CMD.SECRETS TXT Secrets Command
8E8–8EFh
TXT.CMD.NO-
SECRETS
TXT No Secrets Command
8F0–8F7h
TXT.E2STS
TXT Extended Error Status Register
Srlz Default Value Access
000000000000
0000h
RW/L
000000000000
0000h
RW
000000000000
0000h
RW
000000000000
0000h
RO,
RW/L,
RWO
FA
N/A
WO
FA
N/A
WO
FA
N/A
WO
FA
N/A
WO
00000000de44
98a3619fa4f4e
5e30200613d4
RO
a51a6f9e712h
FA
N/A
WO
FA
N/A
WO
000000000000
0000h
RO
Note:
Srlz: Indicates if a serializing step is required by software (for example, a read) before
or after a write to the register. Note that this is referring to serializing at the chipset
hardware level. Since TXT space is memory-mapped, multiple commands or writes can
be enqueued in a back-to-back sequence. If a preceding command or write takes
several clocks to be fully processed, the subsequent accesses may be handled
incorrectly. Therefore, simply serializing these cycles as they leave the processor may
not be sufficient to guarantee that they are appropriately serialized by the time they
are processed in the chipset. A read following the write does guarantee that a
subsequent write is serialized after the first write. FA=Fence after. FB=Fence before.
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Datasheet