AC82G41SLGQ3 Datasheet, PDF (100/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
27
26
25:3
2:1
0
Access
R/W/L
R/W/L
RO
R/W/L/K
R/W/L
Default
Value
0b
0b
000000h
00b
0b
RST/
PWR
Core
Core
Core
Core
Core
Description
128MB Base Address Mask (128ADMSK): This bit is
either part of the PCI Express Base Address (R/W) or part of
the Address Mask (RO, read 0b), depending on the value of
bits 2:1 in this register.
64MB Base Address Mask (64ADMSK): This bit is either
part of the PCI Express Base Address (R/W) or part of the
Address Mask (RO, read 0b), depending on the value of bits
2:1 in this register.
Reserved
Length (LENGTH): This Field describes the length of this
region. It provides the Enhanced Configuration Space
Region/Buses Decoded
00 =256 MB (buses 0–255). Bits 31:28 are decoded in the
PCI Express Base Address Field
01 = 128 MB (Buses 0–127). Bits 31:27 are decoded in the
PCI Express Base Address Field.
10 =64 MB (Buses 0–63). Bits 31:26 are decoded in the PCI
Express Base Address Field.
11 =Reserved
PCIEXBAR Enable (PCIEXBAREN):
0 = The PCIEXBAR register is disabled. Memory read and
write transactions proceed as if there were no
PCIEXBAR register. PCIEXBAR bits 35:26 are R/W with
no functionality behind them.
1 = The PCIEXBAR register is enabled. Memory read and
write transactions whose address bits 35:26 match
PCIEXBAR will be translated to configuration reads and
writes within the (G)MCH. These Translated cycles are
routed as shown in the table above.
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Datasheet